BPM Microsystems Device Search

Socket Adapters and Programmers Supporting Silicon Laboratories BGM121N256V2R (ID=477h) LAP(56)

Socket Adapter (click to buy)DescriptionPackageDevices SupportedAdapter Capacity per SiteSockets per Adapter2900L, 3910, 4910, 3928, 3901, 3900, 2900, 4900, 1900
FVX4ASMC56QFNVRAutomated SOCKET MODULE, 56 PIN QFNLAP(56)22, 3 or 41✓

Device Parameters

Device NameSilicon Laboratories BGM121N256V2R (ID=477h)
ManufacturerSilicon Laboratories
Part NumberBGM121N256V2R (ID=477h)
8-bit Bytes266356736.0
Vcc(program)3.3
Set programmingYes
Memory Regions0h-3 FFFFh; FE0 0000h-FE0 07FFh; FE0 4000h-FE0 47FFh;
Electrical EraseYes
PackagesLAP(56)
NotesIMPORTANT:
Device Type:ARM Cortex-M4 32-bit MCU
Device Size:256K-Byte Flash Memory
Algorithm Programming Method:JTAG + Custom bootloader
Memory Organization:
Memory Type Attributes* Included inDefault Range DUT Physical ByteAddress (hex) BPWin Buffer ByteAddress (hex)
Main Flash Block R/W/E Yes 0000_0000 - 0003_FFFF 0000_0000 - 0003_FFFF
User Data Page R/W/E No 0FE0_0000 - 0FE0_07FF 0FE0_0000 - 0FE0_07FF
Lock Bits Page R/W/E No 0FE0_4000 - 0FE0_47FF 0FE0_4000 - 0FE0_47FF
Default Algorithm Range --- --- 0000_0000 - 0003_FFFF 0000_0000 - 0003_FFFF
* R/W/E: readable and rewritable if not locked. Memory ranges can be selected under Device->Settings. Lock Bits Page:
Memory Location Lock Bit Name Lock Bit Description
0FE0_4000 PLW[0] There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers to the last page within a PLW.
0FE0_4004 PLW[1] There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the 32nd page and bit 31 refers to the 63rd page within a PLW.
0FE0_4xxx PLW[N] Thus PLW[0] contains lock bits for page 0-31 in the main block PLW[1] contains lock bits for page 32-63 etc.A page is locked when the bit is 0. A locked page cannot be erased or written.
0FE0_41E8 CLW Word 122 is configuration word Zero. Bit[2] is the pinresetsoft bit. Bit[1] is the bootloader enable bit.
0FE0_41F0 ALW Word 124 is the Authentication Access Port (AAP) lock word (ALW) and the four LSBs of this word are the lock bits.If these bits are 0xF then AAP access is enabled.Locking AAP is irreversible. Once AAP is locked it will be impossible to perform an external mass erase and AAP lock cannot be reset.
0FE0_41F4 MLW Word 125 is the mass erase lock word (MLW). Bit 0 locks the entire flash. The mass erase lock bits willnot have any effect on device erases initiated from the Authenitcation Access Port (AAP) registers.
0FE0_41F8 ULW Word 126 is the user page lock word (ULW). Bit 0 of this word is the User Data Page lock bit. Bit 1 in this word locks the Lock Bits Page.
0FE0_41FC DLW Word 127 is the debug lock word (DLW). The four LSBs of this word are the debug lock bits. If these bits are 0xFthen debug access is enabled.Locking debug access will disable access to the device by the programmer.
Special Device Considerations:
The Erase operation will erase the lock bits page no matter which range is selected under Device->Settings.
Programmer3900
Socket ModulesFVX4ASMC56QFNVR
Device Name with PackageSilicon Laboratories BGM121N256V2R (ID=477h) LAP(56)
Device Name with Package and AdapterSilicon Laboratories BGM121N256V2R (ID=477h) LAP(56) FVX4ASMC56QFNVR

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Server started at 2025-10-24 19:59:38 UTC. Database loaded at 2025-11-30 20:07:47 UTC. All data provided on a best-efforts basis. Prices and specifications subject to change without notice. You may search for an adapter using the following syntax: adapter:ASM48T* or adapter:FX4ASM48TD.