BPM Microsystems Device Search

Socket Adapters and Programmers Supporting STMicroelectronics STM32WB55RGV6TR (Custom 01) (ID=2477h) VFQFPN(68)

Socket Adapter (click to buy)DescriptionPackageDevices SupportedAdapter Capacity per SiteSockets per AdapterAdapter Price3800, 2800, 4800
FVE4ASM68QFNBAutomated SOCKET MODULE, 68 PIN QFNVFQFPN(68)82, 3 or 41$418.00✓
FVE4ASMR68QFNBAutomated SOCKET CARD, 68 PIN QFNVFQFPN(68)82, 3 or 41$497.00✓

Device Parameters

Device NameSTMicroelectronics STM32WB55RGV6TR (Custom 01) (ID=2477h)
ManufacturerSTMicroelectronics
Part NumberSTM32WB55RGV6TR (Custom 01) (ID=2477h)
8-bit Bytes536838272.0
Vcc(program)3.3
Set programmingYes
Memory Regions700 0000h-70F FFFFh; 800 0000h-80F FFFFh; 1FFF 7000h-1FFF 73FFh;
Electrical EraseYes
PackagesVFQFPN(68)
NotesIMPORTANT:
Device Type: ARM 32-bit Cortex-M4 + Cortex-M0+ CPU cores
Device Size: 1M-Byte Flash + 1K-Byte OTP
Algorithm Programming Method:SWD
Memory Organization:
Memory Type

Attributes(*)

 Included in Default Range (Y/N) DUT Physical Byte Address(hex)(if this area is selected/activated) BPWin Buffer Byte Address(hex)
Flash Memory (FUS Upgrade) R/W/E No 0800_0000 - 080F_FFFF 0700_0000 - 070F_FFFF
Flash Memory R/W/E Yes 0800_0000 - 080F_FFFF 0800_0000 - 080F_FFFF
OTP Memory R/W No 1FFF_7000 - 1FFF_73FF 1FFF_7000 - 1FFF_73FF
Option Bytes R/W/E No 1FFF_F800 - 1FFF_F87F 1FFF_F800 - 1FFF_F87F
Default Algorithm Range --- --- 0800_0000 - 080F_FFFF 0800_0000 - 080F_FFFF
* R:Read only W: One time programmable (OTP) R/W: readable and one time programmable (OTP) R/W/E: readable and rewritable if not locked. Any configurations listed under Device-Specific" in the menu item Device-> Settings will be written to the DUT during "Program" operation. Special Device Considerations:
1.This custom algorithm enables support for updating the FUS and installing the wireless stack firmware via the FUS.This algorithm has only been tested with devices with FUS version 1.2.0.
2.FUS firmware updating can be enabled under Device->Settings.This will enable updating the FUS firmware during the Program operation if the range is included.The Program operation will verify the FUS firmware data in the flash before installing it.
3.For the FUS upgrade BPWin Data Buffer addresses 700_0000h - 70F_FFFFh map to 800_0000h - 80F_FFFFh on the device.For example if loading the FUS firmware to 80E_C000h in the flash load the file at 70E_C000h in the BPWin Data Buffer.
4.All other operations will not use the FUS firmware data.
5.Wireless stack firmware updating can be enabled under Device->Settings.This will enable deleting the current firmware if installed during the Erase operation.This will also enable installing the new firmware at the end of Verify during EPV.Stand-alone Verify will not install the new firmware.
4.The Flash Memory range accessible to CPU1 will vary depending on the size of the wireless stack firmware.This algorithm cannot directly access the Flash Memory range reserved for CPU2.
6.This algorithm will verify the wireless stack firmware data in the flash prior to installing.After installing the firmware this algorithm will confirm that the device reports non-zero firmware version and size.
7.If the wireless stack firmware update option is enabled stand-alone Verify will not verify the firmware data.It will skip any data in the range that is reserved for CPU2 and confirm that the device reports non-zero firmware version and size.
8.If the wireless stack firmware update option is disabled stand-alone Verify will attempt to verify any non-blank data.This will include any non-blank data that is in the range reserved for CPU2 which will cause the device to fail.In this case the range reserved for CPU2 should be left blank in the Data Buffer.
9.Read and Compare operations will return all 0xFF values for the range reserved for CPU2.This will cause Compare to fail if the Data Buffer has any non-blank data in this range.
10.Blank Check will only check the range accessible to CPU1 as reported by the device. The range reserved for CPU2 will be skipped.
11.Setting RDP to Level 2 (CCh) will disable the debug interface. This will cause all subsequent operations to fail.
12.Setting RDP to Level 1 (non-AAh non-CCh) or enabling PCROP will make all or portions of the available Flash Memory unreadable.These settings can be erased.
13.The Erase operation will erase the entire Flash Memory that is accessible to CPU1.The Option Bytes will be reset to the default values except PCROP_RDP will be cleared.
14.If modifying the boot settings in the Option Bytes to boot from the Flash Memorythe code may prevent Stand-alone Verify from confirming that a wireless stack is installed.
15.When setting the Option Byte settings under Device->Settings please make sure to set any reserved bits to 0.The reserved bits will be masked during all operations but incorrectly setting them may cause false failures.
"
Programmer2800
Socket ModulesFVE4ASMR68QFNB, FVE4ASM68QFNB, FVE4ASM68QFNB, FVE4ASMR68QFNB
Device Name with PackageSTMicroelectronics STM32WB55RGV6TR (Custom 01) (ID=2477h) VFQFPN(68)
Device Name with Package and AdapterSTMicroelectronics STM32WB55RGV6TR (Custom 01) (ID=2477h) VFQFPN(68) FVE4ASMR68QFNB, FVE4ASM68QFNB, FVE4ASM68QFNB, FVE4ASMR68QFNB

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Server started at 2025-05-21 04:36:43 UTC. Database loaded at 2025-07-02 04:45:09 UTC. All data provided on a best-efforts basis. Prices and specifications subject to change without notice. You may search for an adapter using the following syntax: adapter:ASM48T* or adapter:FX4ASM48TD.