BPM Microsystems Device Search

Socket Adapters and Programmers Supporting Infineon(Siemens) IRPS5401MTRPBF(FVX4G2) QFN(56)

Socket Adapter (click to buy)DescriptionPackageDevices SupportedAdapter Capacity per SiteSockets per Adapter310
FVX4G2ASMR56LAPSAutomated SOCKET CARD, 56 PIN LAPQFN(56)12, 3 or 42✓

Device Parameters

Device NameInfineon(Siemens) IRPS5401MTRPBF(FVX4G2)
ManufacturerInfineon(Siemens)
Part NumberIRPS5401MTRPBF(FVX4G2)
8-bit Bytes131072.0
Vcc(program)5.0
Set programmingnan
Memory Regions0h-1 FFFFh;
Electrical Erasenan
PackagesQFN(56)
NotesIMPORTANT:
Device Type: Infineon Flexible Power Management Unit
Device Memory Type: Configuration Registers
Algorithm Programming Method: PMBus
Supported Data File Format: Single image three column configuration file
Serialization Supported: No
Memory Organization:
Memory Type

Attributes(*)

 Included in default Range (Y/N) DUT Physical Byte Address(hex)(if this area is selected/Activated) BPWin Buffer Byte Address(hex)
Configuration Registers R/W/E Yes 0000 - 17FF Determined by data file
Default Algorithm Range --- --- 0000 - 17FF Determined by data file
* R/W/E: readable and rewritable if not locked. Configuration Register Mapping:
SectionSwitcherRegister Range(hex)Enable Register(hex) and Bit
CNFG---0000 - 0001---
UserCommon0020 - 003A---
UserA0420 - 043F0600 - 06FF0700 - 07FF0038[0]
UserB0820 - 083F0A00 - 0AFF0B00 - 0BFF0038[1]
UserC0C20 - 0C3F0E00 - 0EFF0F00 - 0FFF0038[2]
UserD1020 - 103F1200 - 12FF1300 - 13FF0038[3]
UserLDO1420 - 143F1600 - 16FF1700 - 17FF0038[4]
Special Device Considerations:
1. Programming each section (CNFG User) can be enabled or disabledfor Program and Verify operations under Device->Settings.
2. The CNFG section is limited to five image writes.If the CNFG section is enabled and there are no more write attempts the Program operation will fail.
3. The User section is limited to 26 image writes.If the User section is enabled and there are no more write attempts the Program operation will fail.
4. The CNFG section should be programmed at least once.Otherwise the User section may not verify correctly.
5. This algorithm will only program and verify the register rangeslisted in the Configuration Register Mapping table above.The masks in the data file will determine which bits to verify.
6. By default all switcher registers will be verified. If register 0038h is specified in the data filethe data there will be used to determine which switcher registers to verify.See the Configuration Register Mapping table above for which bit corresponds to which switcher.A bit value of 0b will enable that switcher and 1b will disable it.
7. Operations on the TRIM section are not supported.
8. When programming the algorithm selects the first unprogrammed imagefor each of the CNFG and USER sections if included.
9. Verify during EPV will verify the CNFG and USER images that are programmed if included.Stand-alone Verify may fail if a higher numbered image was previously programmed.
10. Check MTP operation checks how many writes are left in the USER/CNFG sections.
"
Programmer310
Socket ModulesFVX4G2ASMR56LAPS
Device Name with PackageInfineon(Siemens) IRPS5401MTRPBF(FVX4G2) QFN(56)
Device Name with Package and AdapterInfineon(Siemens) IRPS5401MTRPBF(FVX4G2) QFN(56) FVX4G2ASMR56LAPS

BPM Device Programmers Support Devices from 237 Manufacturers

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Server started at 2026-10-13 16:03:45 UTC. Database loaded at 2026-10-23 16:12:02 UTC. Device list loaded at 2026-10-23 16:12:17 UTC. All data provided on a best-efforts basis. Prices and specifications subject to change without notice. You may search for an adapter using the following syntax: adapter:ASM48T* or adapter:FX4ASM48TD.