| Socket Adapter (click to buy) | Description | Package | Devices Supported | Adapter Capacity per Site | Sockets per Adapter | 310 |
|---|---|---|---|---|---|---|
| FVX4G2ASMR08LAPA | Automated SOCKET CARD, 8 PIN WSON | WSON(8) | 3 | 2, 3 or 4 | 2 | ✓ |
| Device Name | GigaDevice Semiconductor Inc. GD25Q64EWIGR (ID=4017h) |
| Manufacturer | GigaDevice Semiconductor Inc. |
| Part Number | GD25Q64EWIGR (ID=4017h) |
| 8-bit Bytes | 8401920.0 |
| Vcc(program) | 3.3 |
| Set programming | Yes |
| Memory Regions | 0h-7F FFFFh; 80 1000h-80 13FFh; 80 2000h-80 23FFh; 80 3000h-80 33FFh; |
| Electrical Erase | Yes |
| Packages | WSON(8) |
| Notes | IMPORTANT: GD25Q64EWIGR: 64Mbit SPI NOR WSON8 6x5mm 2.7-3.6V. Standard SPI with CPU-domain DutR8 gang programming. Main flash and default range: 000000-7FFFFF. Three 1024-byte security registers are mapped to 801000-8013FF 802000-8023FF and 803000-8033FF; physical SPI addresses are 001000-0013FF 002000-0023FF and 003000-0033FF respectively. Add their ranges explicitly when required. Erase does not clear OTP locks. LB3:LB1 permanently lock the corresponding security registers. Default is 0. SRP1 special-order protection is not offered for the normal G order code. Configure options are applied during Program regardless of selected range. Serialization is supported by the native CPU DutR8 packet-stream path. |
| Programmer | 310 |
| Socket Modules | FVX4G2ASMR08LAPA |
| Device Name with Package | GigaDevice Semiconductor Inc. GD25Q64EWIGR (ID=4017h) WSON(8) |
| Device Name with Package and Adapter | GigaDevice Semiconductor Inc. GD25Q64EWIGR (ID=4017h) WSON(8) FVX4G2ASMR08LAPA |